FPGA-based compact differential evolution

This paper presents a hardware architecture for compact Differential Evolution (cDE) in FPGA. The proposed architecture includes a novel hardware Gaussian random number generator (GRNG) suitable for real-value compact evolutionary algorithms. The algorithm and hardware architecture of the proposed GRNG are presented. The FPGA-based cDE is designed and implemented. The set of standard benchmark problems are used to test the proposed hardware cDE. The experimental results demonstrate the performance of the proposed hardware architecture in term of speed and FPGA resources.