Charge-Based Modeling of Double-Gate and Nanowire Junctionless FETs Including Interface-Trapped Charges

Nanowire (NW) semiconductors are interesting devices for being used as sensors. Such NWs are doped silicon channels with electrical contacts at both ends, which is a kind of the so-called junctionless (JL) device. However, in contrast with the state-of-the-art CMOS FETs, a relatively high concentration of traps is expected when using these architectures as biosensors, since their surface is supposed to be in contact with chemicals and gases. A major concern is that these traps will substantially modify the charge-voltage characteristics, thus asking for improvement of basic compact models. In this respect, we have included the effect of interface traps in NW and double-gate JL devices through a charge-based model that has been developed previously. The soundness of this approach is confirmed by extensive comparisons with numerical technology computer-aided design simulation, while the analytical formulation helps understanding the most relevant parameters of the traps with respect to the technology.