Dual-Gate JFET Modeling II: Source Pinchoff Voltage and Complete $I_{\textrm {ds}}$ Modeling Formalism

This paper studies the phase diagram of source pinchoff of dual-gate JFETs and presents a source pinchoff modeling formalism that is smooth across the phase boundaries. Based on this, an I
_ds
model is derived, which is numerically robust for any value of top- and bottom-gate voltages. The method is applied to both the exact model for I
_ds
and an approximated form based on mid-point-potential linearization, and is verified by comparison with numerical simulation. Modeling of short-channel effects is included.