Reliability of Highly Stable Amorphous-Silicon Thin-Film Transistors Under Low Gate-Field Stress—Part I: Two-Stage Model for Lifetime Prediction

To predict reliability, an analytical model for drain current degradation in amorphous-silicon (a-Si) thin-film transistors (TFTs) is developed for the low-gate-field region, where defect creation dominates the threshold voltage shift. Starting with fundamental models where the local threshold shift depends on the local channel electron density, a stretched exponential expression for current degradation in linear and saturation modes is derived and related to an effective threshold voltage. The model was used to predict room temperature stability from accelerated stress up to 140 °C in highly stable TFTs with hydrogenated a-Si channels and silicon nitride (SiN
_x
) gate insulators. For high temperatures and long times at all temperatures, defect creation dominated the decay. A “unified” stretched exponential fit, in which a single fitting parameter is used to convert time into “thermalization energy,” unifies drain current decay at different temperatures into a single curve. At short times near room temperature, a second mechanism ascribed to charge trapping also contributes to the initial degradation. This contribution is attributed to charge trapping in the SiN
_x
gate insulator and can also be fitted with a stretched exponential expression. A two-stage model that combines both mechanisms is used for best predictions of room temperature stability. Part II of this paper will show that this two-stage model facilitates the optimization of the fabrication of a-Si TFTs with very high stability.