Performance and Device Design Based on Geometry and Process Considerations for 14/16-nm Strained FinFETs

The multigated architecture of FinFETs appear attractive for continued CMOS scaling with the addition of discrete fin sizing that brings a new variable into the design. In this paper, a comprehensive 3-D simulation on 14/16-nm advanced-process FinFET under geometric and process considerations was presented in order to achieve the best possible performance with minimal penalty. Geometric designs, specifically the width and height of the fins as well as the channel lengths, were imposed onto the FinFET, and the impact on the performance merits and device's characteristics was analyzed. The influence of stress engineering, metal gate work function (WF), and doping concentration was further explored for an allowable leakage limit. The simulation suggests that the process-induced stress can boost the 14/16-nm FinFET drain current up to two or three times. It was also found that the channel length is the most critical geometric parameter to affect the performance of both the pFinFET and nFinFET, of which 60% and 50% increases in its respective drain current were observed as the channel length is scaled from 35 nm to 15 nm. In addition, a change in metal WF is found to be the most effective method for the adjustment of threshold voltage.