A comparison of CMOS chip to chip interconnections: vertical optical through-Si links versus high density electrical interconnect

High density (HDI) electrical interconnections and vertical optoelectronic interconnections (OE) through-Si links for 3D computational systems have been modeled, and compared and contrasted in the areas of latency, size, and power dissipation. Based upon STA Roadmap projections, which indicate interconnection as a challenge area for coming generations of electronics, optoelectronics may serve a role in chip to chip interconnections for massively parallel computational systems.