A planarization technology using a bias-deposited dielectric film and an etch-back process

A perfect planarization technology with bias deposition of the interlevel dielectric and etch-back process including double photoresist coating has been developed. Firstly, the interlevel SiO/sub 2/ was deposited by bias sputtering that planarizes only the SiO/sub 2/ surface on fine aluminum lines. Subsequently, to remove SiO/sub 2/ plateaus on wide aluminum lines caused by bias deposition, the second planarization by etch-back was performed. Owing to the leveling by the double-layer photoresist coating, a precisely controlled and uniform etch-back was possible, resulting in a nearly planar surface (i.e. the roughness less than approximately 100 nm) over all device areas on a 6-in wafer. This technology is effective for realizing three or more level submicrometer interconnections in future VLSI systems.<
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