A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass $\Delta \Sigma $ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability

A center frequency reconfigurable continuous-time bandpass ΔΣ modulator is implemented in 65 nm CMOS. A new duty-cycle-controlled DAC scheme facilitates center frequency reconfiguration, and also reduces power consumption and die area by halving the total number of DACs in the modulator. A prototype sixth-order modulator, sampling at 800 MS/s, achieves a measured 69 dB SNDR over a 25 MHz bandwidth around a 200 MHz center frequency. The center frequency of the prototype bandpass ΔΣ modulator can be varied from 180 to 220 MHz. The total power consumption is 35 mW and the die area is 0.25 mm
²
. This modulator scheme facilitates receivers that support multiple channels over a wide range of frequencies.