A new implant-through-contact method for fabricating high-voltage TFTs

A process to fabricate offset-gate thin-film transistors for high-voltage (i.e. >60-V) large-area applications is demonstrated. In contrast to the conventional method where an additional masking step is applied to mask the channel and the offset regions, the n/sup +/ source-drain implant is performed in the present process only after contact is open, and is therefore self-aligned to the contact. The offset-gate transistors are achieved by proper transistor layout where the contact-to-gate distance equals the designed n/sup +/-to-gate offset. In addition to saving one masking count as compared with the conventional method, the implant-through-contact method also features a self-aligned field-plant structure and smaller transistor layout area.<
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