A gray code based time-to-digital converter architecture and its FPGA implementation

A glitch-free time-to-digital converter (TDC) based on Gray code is presented. This architecture can reduce hardware, power consumption, as well as chip area significantly compared to a flash type TDC, while keeping comparable performance and glitch-free characteristics. Its proof-of-concept prototype was implemented on FPGA, and the measurement and simulation results validate the effectiveness of the proposed architecture.