A fine-grained configurable cache architecture for soft processors

The ever increasing density and performance of FPGAs, has increased the importance and popularity of soft processors. The growing gap between the speed of processors and memories can partly be compensated through memory hierarchy. Since memory accesses follow a non-uniform distribution, and vary from one application to another, variable set-associative cache architectures have emerged. In this paper, a novel cache architecture, primarily aimed at soft processors, is proposed to address the variable access demands of applications, through dynamically configurable line-associativity, with no memory overhead. The FPGA implementation of the proposed architecture achieves an average miss count reduction of 70% compared to the direct-mapped cache which translates in 17% improvement in IPC, on 11 benchmarks.