A new leakage mechanism of Co salicide and optimized process conditions [for CMOS]

We have clarified a new leakage mechanism in Co salicide process for the ultrashallow junctions of 0.1-/spl mu/m CMOS devices and revealed the optimum Co salicide process conditions for minimizing the leakage current. We found that leakage currents flow from many localized points that are randomly distributed in the function area. We successfully verified our localized leakage model via Monte Carlo simulation. We identified abnormal CoSi/sub x/ spikes under the Co silicide film, as being the origin of the localized leakage current. These CoSi/sub x/ spikes grow rapidly only during annealing between 400 and 450/spl deg/C for 30 s when Co/sub 2/Si phase is formed. These spikes never grow during annealing at over 500/spl deg/C, and decrease with high temperature annealing. A minimum leakage current results by optimized annealing at between 800 and 850/spl deg/C for 30 s. This is because a trade-off exists between reducing the CoSi/sub x/ spikes and preventing the Co atom diffusion from Co silicide film to Si substrate, which begins at annealing above 900/spl deg/C.