Multibit resonant tunneling diode SRAM cell based on slew-rate addressing

We propose and demonstrate a resonant-tunneling diode (RTD) based memory cell in which N bits are stored in a series combination of N RTDs without internal node contacts. The slew rate of an applied voltage signal determines the circuit switching dynamics and allows addressing of the bits. We verify slew rate dependent switching order of up to four series RTDs experimentally and through SPICE simulation incorporating a physics-based RTD model. The new addressing scheme allows N bits to be stored in a stack of N vertically integrated RTDs compared to log/sub 2/ (N) bits in previous demonstrations. We demonstrate a two-bit two-RTD static memory cell based on the new method.