A low-voltage line driver for digital signaling interface

This paper describes a CMOS line driver that operates from a 3 V power supply and delivers a peak current of about 100 mA to the load. The novel features of the circuit are high power efficiency, an output pulse shape and amplitude independent of power supply and temperature variations, and the ability to handle abnormal load termination conditions. The circuit has been designed in a 0.9 /spl mu/m CMOS technology and does not require any low-threshold devices.