PIN-preamp module and CDR-DMUX constituting a receiver for short-haul links up to 3.5 Gb/s

A 3.5-Gb/s two-chip receiver consisting of a preamp and a gate-array-based clock and data recovery demultiplexer (CDR-DMUX) is fabricated in a 25-GHz Si bipolar process. The preamp is mounted within a 5-mm-diameter PIN-diode package. Measurements show >10 dB excess gain if the input referred offset of the CDR is restricted to <1.5 mV. The gate array is utilized to <30% and mounted in a 100-pin plastic package. The CDR features an asynchronous-digital-hierarchy-compatible loss-of-signal detection tripping at a bit error rate >10/sup -3/. The chips dissipate 210 and 1500 mW from +5.0- and -4.5-V supplies, respectively.