Optimal memory selection for low power embedded systems

We present a mathematical model to optimize on-chip memory configurations for minimal power consumption. Splitting memory into sub-units and mapping frequently accessed addresses to small memories reduces power consumption. We have defined an integer linear programming model to solve the combined problem of finding an optimal selection of memory instances and an optimal mapping of application segments. Yielding power reductions of up to 82% for instruction memory and 73% for data memory, makes the model a valuable tool for system synthesis.