Extending Microprocessor Trace Hardware for Fault Injection

This paper proposes a novel concept for fault injection based on the trace interface, which is originally intended for software debugging. Initially, an introduction to fault injection is presented. Following the illustration of the underlying infrastructure, requirements for the integration of fault injection are developed leading to the selection of instrumentation-based techniques. On this basis, this document details the implementation of a technique on register transfer level, supporting five fault models. Controllability and observability of faults are specified.