Minimum Power in Analog Amplifying Blocks: Presenting a Design Procedure

This tutorial presents a design procedure to establish such optimum power levels. It is developed for a single transistor. The BSIM6/EKV models are used as they greatly simplify this design procedure. and this is why they are discussed first in their shortest possible form. The next section gives the actual optimization procedure, which is then repeated for CMOS technologies down to 5 nm.