Implementation of a broadband equalizer for high-speed wireless data applications

A broadband wireless technique based on equalized quaternary phase shift keying (QPSK) proposes to increase the data rate capabilities of current mobile radio links from tens of kbps to several Mbps. The key-enabler is a reduced complexity decision feedback equalization technique that provides a delay spread tolerance in mobile broadband channels of up to several tens of symbol periods. This paper presents an implementation study that includes a complexity estimation of this equalization technique. In doing so, we also introduce a new cyclic correlation technique that minimizes the packet overhead required for channel estimation. The decision feedback equalizer (DFE) is implemented in VHSIC hardware description language (VHDL). Design verification, which compares the performance of the implemented DFE with that obtained from computer simulation, confirms the feasibility and practicality of the proposed equalizer concept. Complexity estimates are provided for different design options. An optimum design yields a required gate count of approximately 600 K gates and a power consumption of about 0.6 W.