Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs

Increased functional density with shrinking technology could result in escalating power supply noise (PSN)-induced failures in the field. Furthermore, the low correlation between system-level functional test and production test is making it difficult to better screen parts that would fail in the field due to PSN. To address these issues, in this paper, we present a fully digital on-chip distributed sensor network to continuously monitor the PSN profile across the chip and generate a trace for diagnosis of any noise-induced failure at silicon validation, structural test, system test, and functional operation phases of system on chips (SoCs). The sensors capture PSN at a fine granularity and store the SoC's critical status bits. The sensor offers easy access and control with the aid of scan chains. The sensor network has been designed in the 28-nm standard cell library, and its performance is demonstrated in the physical design of OpenSPARCT1 multicore processor SoC.