Design Guideline for Complementary Heterostructure Tunnel FETs With Steep Slope and Improved Output Behavior

In this letter, design guideline for complementary heterostructure tunnel FETs (C-HTFETs) is proposed based on the insight into the tradeoff between n-type and p-type HTFETs optimization. For the first time, the contradiction of source/channel material selection between n-type and p-type HTFETs is addressed, indicating that HTFETs integrated on the same materials system cannot achieve optimized n-type and p-type devices simultaneously. Optimized complementary III-V HTFETs based on two different source/channel materials systems are studied as design examples for further validation of the proposed design guideline, exhibiting both steep sub-threshold swing and improved output behavior in the n-type and p-type HTFETs. The conclusions are helpful to the prospective C-HTFETs design for low-power complementary logic applications.