Developing a power loss factor for PWM-VSI inverters

Due to the improved capabilities available in controlled switching devices, higher frequency switching is now possible in voltage fed inverters, which are used in adjustable speed drives and uninterruptable power supplies. This increases the importance of considering power loss in inverters, especially switching losses. This paper aims at developing a simple technique for comparison between PWM methods with respect to the power loss that is generated in inverters. This technique is applied to different space vector modulation methods. It is found that the space vector modulation method expected to generate the lowest overall power loss is the one with a half-wave symmetrical clamp in the fundamental period.