Clock switching: a new design for current testability (DcT) method for dynamic logic circuits

Using an I/sub ddq/ test methodology on circuits with dynamic logic tends to be problematic, mainly due to charge leakage related problems. A new Design for current Testability (DcT) method has been developed, which overcomes these problems by switching the circuit into a static mode during test. The method referred to as clock switching is applicable to both domino logic and True Single-Phase Clock (TSPC) circuits. This paper shows that this technique can lead to higher levels of I/sub ddq/ testability and a reduced test vector set for the detection of bridging faults.