Killer defects control on patterned wafers for the sub quarter micron interconnect formation process

Statistical yield modeling has become very practical and effective for defect control since CMP was first applied to the multilevel metallization process in order to achieve surface planarity. This paper presents a study of the defect size to be controlled for the sub-quarter micron interconnect formation process with CMP planarization by estimating the statistical model parameters from experimental data. First, the size distribution, F(x)=ax/sup b/, of defects on PVD processed wafers is obtained. Secondly, the defect sensitivity on sub-quarter micron line and space patterns is estimated. Thirdly, the killer probability during the interconnect formation process is calculated. Finally, we discuss the detection sensitivity of automatic inspection tools for patterned wafers to control killer defects for the sub-quarter micron interconnect formation process.