Process Development and Optimization for 3 $\mu \text{m}$ High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 μm top entrant critical dimension and 50 μm depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3 μm TSV etch, dielectric liner coverage, metal barrier and seed layer coverage, and copper electroplating.