Low power-area Pass Transistor Logic based ALU design using low power full adder design

With increasing contribution of leakage in total active power, run-time leakage control techniques are becoming extremely important. The Pass-Transistor Logic (PTL) is a better way to implement circuits designed for low power applications. As the technology is growing pass transistor logic has gained the prominent importance. In this design of 1 bit ALU, PTL technology has been deliberately implemented. The Boolean equations have been modified in order to reduce the transistor count, and also reuse of hardware has also been achieved. In this research work a new design of low power 6Transistors based 1 bit full adder circuit has been used. This full adder circuit consumes less power with maximum of 93% power saving compared to conventional 28T design and 80.2% power saving compare to SERF design[4] without much delay degradation in case of 6T full adder design. Finally ALU circuit has been designed using 6T full adder cell and Pass Transistor Logic based logic blocks such as AND, OR, XOR and the results have been compared to earlier designs in [1, 2]. The simulation results indicate that, for the 65nm CMOS technology the ALU total energy is reduced by 98.28% with minimal delay degradation when compared to earlier design in [1] and 97.20% when compared to earlier design in [2]. The entire simulations have been done on 65 nm single n-well CMOS bulk technology, in virtuoso platform of cadence tool with the supply voltage 1.2V and frequency of 100MHz.