A pipelined CORDIC architecture and its implementation in all-digital FM modulator-demodulator

COordinate Rotation DIgital Computer (CORDIC), is an algorithm that is used to perform trigonometric-related calculations. CORDIC is often utilized in the absence of hardware multiplier since this algorithm requires only addition, subtraction, bit shifting, and lookup table. This paper provides an implementation of CORDIC algorithm using pipelined architecture. The pipelined CORDIC is then used in an all-digital FM modulator-demodulator. All designs are implemented in Verilog and synthesized by using Altera Quartus software with DE2-70 FPGA target board. The proposed design consumes 1,103 logic element, latency 33.32 ns, and maximum frequency 420.17 MHz. The overall system including FM modulator-demodulator utilizes 3,911 logic elements, latency 233.33 ns, and maximum frequency 60 MHz.