Exploiting fine- and coarse-grain parallelism in embedded programs

Due to the technological advances, mapping of embedded applications onto single-chip multiprocessor systems becomes a feasible and very interesting option. What is needed is an environment that supports the designer in transforming an algorithmic specification into a suitable parallel implementation. In this paper we present the results of our experiments with one such an environment, which we developed within our laboratory. As opposed to the existing ones, our framework semi-automatically exploits different kinds of coarse and fine-grain parallelism from an embedded program written in ANSI C. It employs functional pipelining and data set partitioning simultaneously with source-to-source program transformations to obtain the most advantageous hierarchical parallelizations. This combination results in high speedups for all tested benchmarks.