On finding undetectable and redundant faults in synchronous sequential circuits

We describe a time-efficient procedure for identifying undetectable and redundant faults in a synchronous sequential circuit, without using a sequential circuit test pattern generator. The proposed procedure is based on the use of a limited length iterative logic array model of the circuit, and has two phases. In the first phase, faults that will not be proved to be undetectable are identified. In the second phase, undetectable faults are identified out of the remaining faults using a combinational circuit test generator. Sequential static learning on the fault-free circuit and a subset of unreachable states are used in the proposed procedure to increase the amount of information available when considering an iterative logic array model of limited length. An undetectable fault in a synchronizable circuit that leaves the faulty circuit synchronizable is identified as a redundant fault. Experimental results presented in this work demonstrate the effectiveness of the proposed techniques in finding undetectable and redundant faults. Larger numbers of undetectable and redundant faults are found compared to earlier works.