Area minimization of redundant CORDIC pipeline architectures

The CORDIC algorithm is used in many fields of signal processing for computation of elementary functions. Its main advantages are versatility and simplicity. When implemented in a word parallel pipeline it yields the highest possible throughput. However this solution is accompanied with increased hardware complexity and chip area requirements. The goal of this paper is to develop redundant CORDIC pipeline architectures yielding very low chip area. The speed does not decrease at all when compared with other proposals. Our novel architectures result in the smallest redundant CORDIC implementation known to the authors. It also exhibits considerably less gate switching activity thus also reducing power consumption.