VLSI circuit complexity and decoding performance analysis for low-power RSC turbo-code and iterative block decoders design

A VLSI circuit complexity analysis for low-power decoder designs is presented. Two low-complexity adaptive decoder architectures incorporating the recursive systematic codes (turbo-codes) and block-codes are considered in this paper. The system performance degradation due to the algorithm approximations for realizing the low complexity decoders is also investigated. The decoders are implemented with 0.6-/spl mu/m CMOS standard cell technology where their power dissipation and size information are obtained. Furthermore, the issues concerning the throughput and latency of the decoder architectures are discussed. This study provides insights into system design trade-offs involving low-power VLSI decoders for portable wireless mobile communication systems.