Hot-carrier effects and reliable lifetime prediction in deep submicron N- and P-channel SOI MOSFETs

Hot-carrier effects are thoroughly investigated in deep submicron N- and P-channel SOI MOSFETs, for gate lengths ranging from 0.4 /spl mu/m down to 0.1 /spl mu/m. The hot-carrier-induced device degradations are analyzed using systematic stress experiments with three main types of hot-carrier injections-maximum gate current (V/sub g//spl ap/V/sub d/), maximum substrate current (V/sub g//spl ap/V/sub d//2) and parasitic bipolar transistor (PBT) action (V/sub g//spl ap/0). A two-stage hot-carrier degradation is clearly observed for all the biasing conditions, for both N- and P-channel devices and for all the gate lengths. A quasi-identical threshold value between the power time dependence and the logarithmic time dependence is also highlighted for all the stress drain biases for a given channel length. These new findings allow us to propose a reliable method for lifetime prediction using accurate time dependence of degradation in a wide gate length range.