0.5-/spl mu/m CMOS circuits for demodulation and decoding of an OFDM-based digital TV signal conforming to the European DVB-T standard

In the context of digital terrestrial TV based on the DVB-T standard, four 0.5-/spl mu/m CMOS IC's (IC1-IC4) are presented. IC1 integrates an 8-K fast Fourier transform for orthogonal frequency division multiplexing demodulation, IC2 performs channel estimation/correction, and IC3 is a forward error corrector implementing a Viterbi and a Reed-Solomon decoder. IC4, which is based on a digital signal-processing core, performs the synchronization tasks of the complete receiver. These four chips have been designed and manufactured using a 0.5-/spl mu/m, 3,3-V, triple-metal CMOS process. Their global complexity is about 500 kgates of standard cells and 1.5 Mbits of memory, which represents a total die area of 435 mm/sup 2/ in 0.5 /spl mu/m. The total power dissipation is about 3.5 W when working at nominal frequency. More generally, these four IC's constitute the digital front-end part of a global chipset receiver (specified within the European project DVBird), also including an analog front end and a MPEG2 demultiplexer IC.