A 1.0-GHz single-issue 64-bit powerPC integer processor

The organization and circuit design of a 1.0 GHz integer processor built in 0.25 /spl mu/m CMOS technology are presented, a microarchitecture emphasizing parallel computation with a single late select per cycle, structured control logic implemented by read-only-memories and programmable logic arrays, and a delayed reset dynamic circuit style enabling complex functions to be implemented in a few levels of logic are among the key design choices described. A means for at-speed scan testing of this high-frequency processor by a low-speed tester is also presented.