A generic topology selection method for analog circuits demonstrated on the OTA example

A generic, knowledge-based method for automatic topology selection of analog circuits in a predefined analog reuse library is presented in this paper on the OTA (Operational Transconductance Amplifier) example. Analog circuits of a given circuit class are classified in a topology tree, where each node represents a specific topology. Child nodes evolve from their parent nodes by an enhancement of the parent node's topological structure. Topology selection is performed by a depth-first-search in the topology tree starting at the root node, thus checking topologies of increasing complexity. The decisions at each node are based on solving equations or - if this is not possible - on simulations. The search ends at the first (and thus the simplest) topology which can meet the specification after an adequate circuit sizing. The advantages of the generic, tree based topology selection method presented in this paper are shown in comparison to a pool selection method and to heuristic approaches. The selection is based on an accomplished chip investigation.