Processing and reliability of flip-chip on board connections

Processes with potential for low cost flip-chip on board assembly were investigated in order to populate conventional printed circuit cards directly or to replace wire bonding in ball grid array packages. Overall aspects of wafer bumping, device placement, underfill encapsulation and assembly integrity were addressed. Two types of wafer bumping process were evaluated, involving fine pitch stencil printing of solder pastes directly on wafers and the application of a wire bonding technique to deposit solder ball bumps on connection pads. To determine flip-chip on board process robustness and reliability, test vehicles were designed to accommodate a range of flip-chip dice, of sizes between 3.8 mm and 12.7 mm and with I/O between 21 and 1056. These vehicles allowed monitoring of electrical continuity through bumps connected in series in daisy chains, as well as including power dissipation and temperature sensing devices for thermal measurements and power cycling tests. The results of the evaluations are discussed, covering assessment of bumping process performance in terms of uniformity and pitch capability and the integrity of flip-chip assemblies determined by nondestructive analysis, mechanical testing and thermal shock testing.