Thermal management of packaged IC by experimentally verified finite element modeling

Increasing integration, higher clock frequencies, and trends for building power chips into standard SMT packages increase power densities, thus leading to severe thermal problems. Thermal management using experimentally verified finite element modeling (FEM) can be a helpful tool to solve these problems. In this paper, we present examples (including comparison with measurements) for three types of thermal problems: (a) determination of junction-to-ambient thermal resistances; (b) determination of single pulse transient thermal resistances; (c) prediction of transient temperatures on hot spots during IC development. Excellent agreement of measurements and FE simulations can be achieved with acceptable effort, if three aspects of special importance for each of the problem types are taken into account. These aspects are: (a) correct heat transfer coefficients for convection and radiation on package and board surfaces; (b) fine meshing close to the heat source and good representation of the spatial distribution of heat conductors and heat capacities; (c) exact data on the effective power input of IC, as well as on all geometrical parameters with considerable thermal effects. In the examples presented here, we achieved an agreement of 5-10 % between theoretical and experimental results.