Challenges and opportunities in packaging technology as ICs move toward deep sub-micron

Summary form only given. As ICs move towards deep sub-/spl mu/m technology, over one hundred million transistors can be produced on a single die. The challenge is how best to use these transistors in circuits and systems, as several new challenges are created by deep sub-/spl mu/m technology. This article offers solutions to these challenges with the key focus on integration. The discussion includes integration of high Q inductors with RF chips using flip-chip assembly technology combined with a high resistivity Si substrate and embedded high Q inductors, the use of chip-on-chip assembly to achieve memory and logic integration, the use of embedded passives for simpler mixed signal circuit design and mixed signal/mixed chip technology integration, and combined flip-chip and high density substrate interconnection to support IC I/O counts as high as 1024. The article also looks at manufacturing platforms to achieve the degree of integration which is hard to achieve with single chip integration. The on-chip electrical environment is preserved, and off-chip barriers are removed. The platforms include flip-chip, high density interconnect Si substrates, embedded high Q passives and flexible ball grid array packages, and are designed for low cost/high volume manufacturing. The modules can be multiple chips with interconnect only, multiple chips integrated with embedded passives or single chip integrated with passives, but the final module acts like a single chip electrically. This set of platforms has been dubbed microsystems integration technology.