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Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT | IEEE Conference Publication | IEEE Xplore

Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT


Abstract:

This paper reports a novel material/process-based design for reliability-aware Ge gate stack for the first time. Initially good characteristics of Ge gate stacks do not n...Show More

Abstract:

This paper reports a novel material/process-based design for reliability-aware Ge gate stack for the first time. Initially good characteristics of Ge gate stacks do not necessarily guarantee the long-term device reliability. To overcome the big hurdle, we have investigated the stability of GeO2 network as well as the formation of new high-k. The very robust Ge gate stack with both 0.5 nm EOT and sufficiently low Dit is demonstrated.
Date of Conference: 17-19 June 2015
Date Added to IEEE Xplore: 03 September 2015
Print ISBN:978-4-86348-502-0

ISSN Information:

Conference Location: Kyoto, Japan

References

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