Effect of body-to-source bias on the analog characteristics of 0.35 /spl mu/m partially depleted SOI CMOS for low-voltage low-power mixed-mode applications

A 3.3 V 0.35 /spl mu/m CMOS process, implemented on 8-inch bonded SOI wafers, is investigated for low-voltage low-power analog applications. Enhanced low-power analog performance is demonstrated by applying a forward biased body-source voltage which enables reduced short channel effects and a flatter threshold voltage response as a function of drawn gate length. Furthermore, this paper demonstrates that the onset of fully-depleted (FD) operation as a function of reverse body-to-source bias is highly sensitive to the channel length.