QPSK demodulator using the methodology of automated system-level ASIC design

The design methodology and the basic features of a QPSK digital demodulator fully compliant with the DVB/DSS Recommendations are presented. The ASIC design and development process employs an "automated system-level design scheme" as a new system ASIC design methodology. This paper discusses the nonsynchronized sampling QPSK demodulation algorithm as an illustrative algorithm in order to demonstrate the benefits when developing such an algorithm using a system-level design scheme.