Modeling and Characterization of the Abnormal Hump in n-Channel Amorphous-InGaZnO Thin-Film Transistors After High Positive Bias Stress

Hump characteristics of n-channel amorphous indium-gallium–zinc-oxide (a-InGaZnO) thin-film transistors (TFTs) after positive gate and drain bias stress (PGDBS) are investigated. With the increase of the PGDBS time, we observed not only a shift of the threshold voltage (
$V_{T}$
) but also a generation of the hump in the transfer characteristics. The hump is caused by the localized trapping of electrons in the gate insulator over the gate-source overlap region by the high vertical field during the PGDBS (
$V_{\mathrm {GS}}=30$
,
$V_{\mathbf {DS}}=30$
;
$V_{\mathrm {GD}}=V_{\mathrm {GS}}-V_{\mathrm {DS}}=0$
V). The TFT with a hump after PGDBS is modeled as a series connection of main and parasitic TFTs. The parasitic TFT for the electron trapping at the gate-source overlap region has a higher threshold voltage (
$V_{\mathrm {Tp}}$
) and a shorter effective channel length (
$L_{\mathrm {chp}}\cong L_{\mathrm {ov}}$
) compared with those (
$V_{\mathrm {Tm}}$
and
$L_{\mathrm {ch}}$
) of the main TFT.