Design for test [session summary]

This session contains papers from different areas in ASIC design that focus on design for testability issues. The session starts with an invited paper by Christopher A. Ryan, Texas Instruments, presenting an embedded core test strategy and built-in self-test for systems on a chip. With the increasing number of embedded cores on a single chip the problems to make each core testable also increases. The author presents a core JTAG strategy with BIST and gives examples of its application in an industrial automotive microcontroller. The regular pa.per part starts with a presentation on Built-in Self-Test. It presents a method of test pattern generation using 2-D LFSR structures that generate a pre-computed test vector followed by random patterns. Another paper deals with integrated scheduling and allocation of high-level test synthesis. The authors present a high-level test synthesis algorithm for operation scheduling and data path allocation. Contrary to other works the approach integrates scheduling and allocation by performing them simultaneously. The next pape:r presents a CMOS Low-power mixed A/D ASIC. It describes the principle of radiation detection, the circuit architecture, low power issues, and then addresses built-in test analog subcircuits that have been implemented in the ASIC along with a JTAG module. Finally, test results are presented showing that all the specifications are satisfied. The session ends with a paper on current-testable high-frequency CMOS operational amplifiers. Current-based test stimuli allow detection of some faults which are difficult to detect or are unstable when using conventional voltage-based stimuli. With the presented approach test stimuli selection is simpler since faulty behaviors are observable in the whole frequency band. The impact of the test circuitry, on circuit performance is negligible.