Advanced 0.25-0.18 /spl mu/m fully-planarized 6-level-interconnect CMOS technology for foundry manufacturing

An advanced 0.25-0.18 /spl mu/m CMOS technology with fully-planarized 6-level-interconnect has been developed for versatile, flexible, and fast turn-around foundry manufacturing. A 0.6 /spl mu/m layout pitch has been successfully demonstrated for active, gate poly, and first metal layers. High performance devices with a dual-oxide (65/50 A) approach were developed for 3.3/2.5 V I/O and core circuits on the same chip. In addition, 0.18 /spl mu/m, 40 A Tox transistors are also available for low-power applications at 1.8 V Vcc. Gate-delay is 40 ps at 2.5 V for the 0.25 /spl mu/m device, and 35 ps at 1.8 V for the 0.18 /spl mu/m device. The embedded 6T SRAM cell size is 6.34 /spl mu/m/sup 2/. Considerations in process architecture and device design for foundry manufacturing are also addressed on this 6-level-metal 0.25-0.18 /spl mu/m CMOS technology.