A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits

This paper proposes a multi-bit incremental analog-to-digital converter (ADC) based on successive approximation (SA) for column-parallel readout circuits. The proposed ADC suppresses the random noise and enhances the resolution by embedding the conventional SA ADC with an integrator and decimation filter. In addition, the operating speed is increased through the two-step operations of coarse conversion with the proposed ADC and fine conversion with the embedded SA ADC. A residue fitting method is adopted to adjust the residue voltage to the fine conversion range after the coarse conversion. The proposed ADC with 12-bit resolution was fabricated using a 0.13
$\mu{\rm m}$
CMOS image sensor process with a pixel array that has an image format of 648
$\times$
488 and a pixel size of
$5.6\ \mu{\rm m}\times 5.6\ \mu{\rm m}$
. The measured results show a random noise of 108
$\mu{\rm V}$
, a dynamic range of 60.9 dB, a differential nonlinearity of
$+$
1.02/
$-$
0.34 least significant bit (LSB), and an integral nonlinearity of
$+$
0.64/
$-$
0.54 LSB.