A framework for thermal aware reliability estimation in 2D NoC

Parallel computing challenges in embedded system design results in development of architectures having large number of cores on a single chip. Network on Chip has been developed to manage the on chip communication issues in Chip-multi processor. Downscaling in technology at deep submicron affects the system level reliability, motivating the researchers to consider the long term durability in design approaches. These architectures have experienced thermal and power inconsistencies that eventually affects the reliability of NoC. Recent advancements in technology forces the design engineers to design the thermal and ageing aware reliable system which improves the life time of devices. This paper presents the integrated life time failure models i.e. stress migration and thermal cycle along with existing models such as time dependent dielectric breakdown and negative bias temperature instability. Subsequently, we perform comparative analysis among power models for the accurate estimation of reliability. These estimations reveals that it is possible to model on chip network for parameters which adversely affects the system performance leading to device or system failure. Through our proposed approach we are able to predict more accurate reliability estimation based on more precise power and thermal awareness.