Flexible input transform architecture for HEVC encoder on FPGA

This paper proposes an FPGA architecture for the 1-D forward integer transform of the High Efficiency Video Coding (HEVC), which is the latest video coding standard. The work presents a novel technique which makes the architecture able to compute transform of flexible input combinations. The architecture can support all transform sizes i.e. 4×4, 8×8, 16×16, and 32×32, and all possible input combinations resulting from a residual quad-tree partitioning with uniform throughputs. Configuration encoding scheme is invented to efficiently represent input combinations. The design gives a high throughput of 1,640 Msamples/s independent of input combination, which is sufficient to encode 8K (7680×4320) videos in real-time, 30 fps.