Write and Erase Threshold Voltage Interdependence in Resistive Switching Memory Cells

A statistical dependence of set voltage V
_set
on the preceding reset voltage V
_reset
is observed in resistive memory arrays and explained in terms of two interlocking mechanisms. This dependence can be replicated on a single device by intentionally varying V
_reset
values by various linear voltage ramp rates. The latter mechanism is well modeled under the assumption that a critical heat deposited locally in the filament triggers the rupture of the filament. Mechanisms are proposed to explain the impact of different ramp rates of the reset operation on the ruptured gap in the filament that affect, in turn, the V
_set
value of the subsequent set operation. Based on these observations, a one-time tightening procedure is designed, leading to tightened V
_set
and V
_reset
distributions.