Modeling & PVT characterization of arbitrary ordered VSCP-PLL using an efficient event-driven approach

The charge-pump phase locked loop (CP-PLL) is a mostly used integrated circuit (IC) in various modern electronics applications to perform several functions. Due to its mixed analog and digital nature, often circuit level simulators are used to characterize its overall nonlinear dynamic behavior. Since the existing analytical methods are not efficient to account non-ideal and non-linear effects. Furthermore, considering a CP-PLL for frequency synthesis function, a low and high frequency part result in very long simulation times. Consequently, Spice like electrical simulator do not provide a quick assessment of the overall non-linear dynamic behavior of the CP-PLL. Additionally the PVT (Process, Voltage, and Temperature) variations are the most important aspect of the design flow to achieve a robust system. In this paper, a first ever PVT characterization of arbitrary ordered voltage switch charge pump PLLs (VSCP-PLL) designed at transistor level (TL) using 130nm CMOS process is presented. By extracting the macroscopic behavior and initial conditions, the simulations were performed using an efficient Event-Driven (ED) approach. The PVT characterization results of the ED-approach are very close to the TL-simulations with a good agreement in accuracy and speed-up factor of 60,000 &7,000 for 2
^nd
and 3
^rd
order PLL is achieved respectively.