A New Subthreshold Current Model for Junctionless Trigate MOSFETs to Examine Interface-Trapped Charge Effects

On the basis of the effects of interface-trapped charges on the flat-band voltage, quasi-3-D scaling equation, and Pao-Sah's integral, a novel subthreshold current model is presented for the junctionless trigate (JLTG) MOSFETs to examine interface-trapped charge effects (ITCEs). It indicates that a thin gate oxide can effectively reduce the subthreshold current degradation caused by the ITCEs. In contrast to the thin gate oxide, a thick silicon is required to alleviate the subthreshold current degradation caused by the ITCEs. For the short-channel behavior, the positive-/negative-trapped charges can enhance/alleviate short-channel effects (SCEs) for the device. As opposed to SCEs, the long-channel JLTG transistor suffers severe ITCEs than the short-channel device. Besides, the JL double-gate device with less gate coverage of the channel can reduce more subthreshold current degradation caused by the ITCEs than both the JLTG and JL quadruple-gate devices. Due to its computational efficiency, the model can be easily used to explore the hot-carrier-induced current behavior for the fully depleted JLTG MOSFETs for its memory cell application.